Xilinx Vivado Essentials for the Logic Designer

Description

What you’ll learn
Getting started designing FPGAs with Xilinx Vivado Design Tools

Requirements
Working knowledge of either VHDL or Verilog
Description
Xilinx Vivado can be overwhelming for a logic designer who is creating their first design for a contemporary Xilinx device. This course describes the various design flows, including hdl only flow, block flow and a hybrid of block and hdl. Each flow includes a simulation options, and adding the Integrated Logic Analyzer to a design. We introduce the Vitis SDK to allow the logic designer to create simple test programs, and describe the AXI4-Lite bus which is the most common interface between processor and logic.

Who this course is for:
Beginning Xilinx FPGA Logic Designers

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